Problem at source files generated by Quartus from user’s “platform design” session (qsys).

​Thanks for the file pointers.

My customer, who is using Quartus with VCS, got the errors I described in this post, on these files that are used in his Qsys design.

He claims that it is qsys did these mistakes of overriding Verilog parameter "CB_PCIE_MODE" of module altpciexpav_stif_rx, whose type is the default type (integer) with value 0, with VHDL generic of type string, with value "0".

Is it possible for Qsys to do such typo, or is it eventually a user error?