Altera_Forum
Honored Contributor
16 years agoProblem accessing RAM-memory
Hi all,
I'm trying to access a dualport RAM-unit. It's purpose is to act like a FIFO-buffer. Addresses are written to incremently. Thus, the code I'm using looks like: ram_64_15_write_address <= std_logic_vector(to_unsigned( specific_address, 13)); specific_address := specific_address + 1; In simulation, this process works as it should. However, when I measure the real-life behavior with Signaltap, the signal 'specific_address' is not incrementing at all. Does someone knows the solution to this problem? I am using Quartus II 8.0 web edition. Regards, Tijmen