Forum Discussion
Altera_Forum
Honored Contributor
16 years ago@Daixiwen: yes, the process is triggered by a clock.
@okerol: I have also tried to use an incrementing std_logic_vector, which had thesame behavior: working simulation but malfunctioning real-life behavior. I have solved the problem by not using an address at all: I have used the FIFO-megafunction of Quartus and it's working now. I was using a self-written RAM-function first, then when that didn't work I tried the RAM-megafunction of Quartus. That showed thesame false behavior. For the ones that are interested: In the attachment file I have supplied the interesting piece of code from my file. Also an image file from the signaltap is included which shows the signal 'schrijfadres' (the discussed variable I changed to 'specific_address' for this post) isn't changing at all! Only the least significant bit is changing. Again: in simulation, it works as planned.