problem (?) using shared variables

The main use for shared variables is in test benches

have a look at OSVVM. ORG

the free packages there make extensive use of SHARED VARIABLES

They are also very useful verification packages.

creating good stimulus is often a lot of work & is boring.

SAVE YOURSELF A LOT OF WORK

have a look at intelligent coverage at OSVVM. ORG

Those packages can create intelligent random functional coverage stimulus for you.

With very little effort from you they can create stimulus for all the functions you ask them to cover in your testbench.

They are written by Jim Lewis & he leads the IEEE VHDL standard group who are working on the next version of VHDL after VHDL2008.