problem (?) using shared variables

I am studying a VHDL book. There are a lot of codes in this book and one of them is this. For some of them, I practice some simulation or implement it on board.

This code with shared variables was presented to explain their functioning. Simulating this code, it didn´t present expected results. Curious about this, I posted on forum.

It´s not a matter of choosing or preferring to use anything. I was just interested to understand if it works. If not, how the log files present to me what´s going on.

In future designs I will consider you recommendation regarding clocks. Could you recommend some good books with practical examples of clock enabling?

Regards

Jaraqui