problem (?) using shared variables

All synthesis tools will synthesise it "correctly". I still dont see why you are sticking with shared variables. They are of no benefit in almost all situations (and prone to errors by inexperienced users, as you have found - its not a simulation bug).

On a point about this design - generating a clock like this is not recommended. It can be prone to timing problems from temperature due to the high skew from non-clock nets.

It is recommended to generate clock enables instead, unless this is a slow clock for an external device (and no internal logic).