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Nice coincidence, this gives quite a bit of understanding on the tool itself:
http://www.alteraforum.com/forum/showthread.php?t=32541 However what I'm really interessted in is the things that I can do to close the timing.
From my former ASIC development job, I was used to get the REAL critical paths, work on them (reduce logic levels, pipeline, redesign to be simpler) and there we were, as the critical paths were the critical ones.
However, with FPGA this is highly undeterministic (as explained in above mentioned link). So the question is how to find out the real critical paths that need to be optimized. I feel like adding tons of pipelining to posssibly not-so-critical paths leads to increase the congestion on all other paths.
So how do i find out the relevant critical paths?
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Hi,
I would try to split the design in partitions. First I would implemented only the timing critcal parts. After the timings are met you can lock down the design. Have look to the documentation regarding design partitions. Maybe this could help.
Best regards
GPK
Honored Contributor
