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Altera_Forum's avatar
Altera_Forum
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15 years ago

Priority handling of paths fitting

I'm facing some difficulites to close timing on my Stratix III device right now as am filling in more functionality.

My basic function is a datapath from a sensor to DDR memory and from there, with some (more and more) processing, to an USB device controller.

For the memory connection I use two DDR memory I/F IP as provided by Altera, synchronized as inidcated in AN 462 "Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction". I had no timing issues with this earlier (so I know that it should work), but now critical paths tend to be in there.

Is there a way of constraining certain paths to be fitted by priority to avoid such effects? (as I will not be able to work on the IP paths, but possible might work on paths now fitting well at the cost of the memory I/F ones...)

Regards,

Peter

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Nice coincidence, this gives quite a bit of understanding on the tool itself:

    http://www.alteraforum.com/forum/showthread.php?t=32541

    However what I'm really interessted in is the things that I can do to close the timing.

    From my former ASIC development job, I was used to get the REAL critical paths, work on them (reduce logic levels, pipeline, redesign to be simpler) and there we were, as the critical paths were the critical ones.

    However, with FPGA this is highly undeterministic (as explained in above mentioned link). So the question is how to find out the real critical paths that need to be optimized. I feel like adding tons of pipelining to posssibly not-so-critical paths leads to increase the congestion on all other paths.

    So how do i find out the relevant critical paths?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Nice coincidence, this gives quite a bit of understanding on the tool itself:

    http://www.alteraforum.com/forum/showthread.php?t=32541

    However what I'm really interessted in is the things that I can do to close the timing.

    From my former ASIC development job, I was used to get the REAL critical paths, work on them (reduce logic levels, pipeline, redesign to be simpler) and there we were, as the critical paths were the critical ones.

    However, with FPGA this is highly undeterministic (as explained in above mentioned link). So the question is how to find out the real critical paths that need to be optimized. I feel like adding tons of pipelining to posssibly not-so-critical paths leads to increase the congestion on all other paths.

    So how do i find out the relevant critical paths?

    --- Quote End ---

    Hi,

    I would try to split the design in partitions. First I would implemented only the timing critcal parts. After the timings are met you can lock down the design. Have look to the documentation regarding design partitions. Maybe this could help.

    Best regards

    GPK