Pretty new at this Trying to make a stopwatch

The synthesizer could be confused by the construction you used for the clocked process. A clocked process should always be constructed like this:

process(clk,reset)
  if (reset = '1') then
    signals reset
  elsif rising_edge(clk) -- or (clk'event and clk='1')
    instructions
  end if;
end process;

You shouldn't do anything outside the clocked area except reset. In you code you have multiple conditions where you modify signals outside a clock edge or reset condition. And worse, some outputs of the process aren't defined on some of the paths, so you will create latches. Stick to the model above and it will avoid lots of problems.

Also in FPGAs it isn't recommended to generate a clock the way you do, it can lead to timing problems and strange behaviour due to glitches. It is better to do a clock enable, i.e. to clock your process with the 100MHz clock, and only perform the stopwatch actions when the count signal reaches its limit.