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Altera_Forum
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13 years ago

Preserving WYSIWYG LUT input assignments

I am working on a Stratix III design in which I need to very precisely control delay paths on some outputs from my design. In a previous version of my design, I hand instantiated WYSIWYG cells and u...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I previously came across the arbitrary router changes to WYSIWYG LUT input assignments. http://www.alteraforum.com/forum/showthread.php?t=27284

My conclusion had been, that the inputs don't have full symmetrical routing capability and that's effectively impossible to implement a low level design with input connections at will.

The other explanation would be, that Quartus just isn't prepared to observe low level user assignments and doesn't try to utilize the existing routing capabilities as far as possible.

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That's the thing, it's not trying at all.

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I agree that the second explanation sounds plausible. But in either case, the consequences are similar: There's no effective way to control the selection of LUT inputs than precise and tight timing constraints.