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Altera_Forum
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13 years ago

Preserving WYSIWYG LUT input assignments

I am working on a Stratix III design in which I need to very precisely control delay paths on some outputs from my design. In a previous version of my design, I hand instantiated WYSIWYG cells and u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

That's the thing, it's not trying at all. The WYSIWYG LCELLs only map the functionality, not the path used. The router can do whatever it wants. (Third party synthesis tools map everything to WYSIWYG primitives. They label them "blindly", and if the router had to follow those mappings, designs would quickly become unroutable.) I don't know of any controller way to do this beside an .rcf.