Preserve logic during signal tap

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Dear all,

I have a problem and will be happy to hear your opinion.

Im using Stratix I 25K LE where the FPGA is 90% occupied.

My design is divided to 3 main blocks, one of them is PCI IP using 160MHz clock, and another 2 blocks of caculations.

I have some "bugs" with the design and i would like to debug it with SIgnal TAP. Because i dont have enough logic, i want to take out the non PCI blocks, add signal tap and debug the PCI block.

The problem is that when im taking out the other blocks, some signals that were connected to the PCI block (from the other blocks) are not exist anymore and for example, some state machines in the PCI block are optimized because now the state machine is not able to reach all states.

I would like to preserve the logic in the PCI block so it will never optimized away.

I think of the following:

1. Use incremental compilation for PCI block by define it as partition

2. Add Signal tap

3. Recompile

Do you think its enough or is there other steps i have to perform?

Thanks in advance.

By the way, i know i can use Signal Probe method, but i dont have an external Logic Analyzer right now.

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Hi,

that should work as long you don't have any open input in your PCI block. If you have some you should either that them to a appropriate value or maybe you can use the "In-System Sources and Probes Editor". This would offer your the possibility to change the value during run-time.

Kind regards

GPK