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Altera_Forum
Honored Contributor
18 years agoOne last assignment might be Implement as Output of a Logic Cell, which is more fundamentally what you want. (The registers weren't getting merged or anything like that, it's just the combinatorial logic gets merged as it should). Incremental Compilation isn't really designed for this purpose, so it wouldn't be documented that way. In fact, part of the reason the documentation isn't good for this type of thing is that this is something user's very, very seldom want(the end result is a slower, larger design). But if you're doing "scientific" research then there are reasons you would want this that just aren't commonly documented.
One last thing is that if the mux gets merged into a LUT, it might not hurt what you're evaluating. For example, if you want to evaluate the ALU and not the mux, but the first part of the ALU is a LUT, then having more logic in the LUT doesn't make it slower(i.e. a 2 input LUT isn't necessarily faster than a 4-input LUT, it's more dependent on what input to the LUT is used, which you're not controlling).