Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Preserve_Hierarchical_Boundary Assignment

Hi all, I've got problem working with this assignments. It doesnot seem to work for my design. By observing the RTL View and Technology map view, i find that the components are merged together bu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Ok, This is my circuit:

2 to 1 Multiplexer connected to a ALU unit. I've looked at the signals in the technology map: the mux is merged into the ALU and it disappears. Yes timing is improved by merging that but i don't want that at this stage (for my "scientific" research on estimation of Max Clock Rate).

I'll try the "Design Partition" suggestion and Thank you a lot. I can't get it right from Altera User Guide :(