Honored Contributor
Honored ContributorOne answer, although I can't figure it out completely, is the hierachy contains dynamic, static and IO power, but only for the "Used" luts and routing, but additional power is wasted (especially static power) for unused LUTS in the device.
If you look at all the table values, they break the number up into dynamic, static and routing numbers but not IO numbers. So it's hard to corrlate with the overal numbers. The numbers I'm most interested in is the Current Drawn from Voltage Supplies, and if you total these numbers up, you get much closer to the overall power numbers, but they are still not exact. In any FPGA design, you are loosing some power efficiency due to unused logic elements. This mostly shows up in the static power number. Pete
