Honored Contributor
Honored ContributorHi,
I'w got similar questions. When creating simulation files in the SOPC environment, RTL level simulation files are created (.vhd files, not gate level .vho files). I know that RTL simulation only considers the functionality of a design, where as gate level simulation also takes timing information into consideration (using a compiled netlist). For the PowerPlay power analyser, I would like to acheive High Power Estimation Confidence level for the SOPC system. Inorder to acheive this, the PowerPlay power analyser needs toggling data (collected in a .VCD file) from gate-level simulations. From the Eclipse SBT, the SOPC system is simulated at the RTL level. I create a SW application and I use "Run As" -> "Nios II ModelSim" inorder to run the simulation. This is conveniant, since the SW application provides correct stimulus data for the SOPC/NiosII system, however, I'm not able to acheive High Power Estimation Confidence level On the other hand, The Quartus II compiles the whole project (SOPC + toplevel file that instantiates the SOPC design) and creates a netlist which can be used inorder to run a gate level simulation. However, doing things this way, I don't have a SW application that can be used as stimulus data for the SOPC/Nios II design. If anyone knows of a more conveniant way of acheive High Power Estimation Confidence level for the SOPC system, (or if there is a way of doing this using QSYS), kindly let me know. Saber890
