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Ok, so if I implement 20 times my initial design which consumes 240mW, I should have a power consumption of 20*240mW? It seems to be a lot but it's what I guess after your de0_nano_power.pdf scheme...
Or is it only the core dynamic power consumption which needs to be multiplied by 20?
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There are three things you would need to consider; core static power (which goes up with temperature), core dynamic power, and I/O power.
If you have an evaluation kit, my advice is to run a few hardware tests with your design and a worst-case toggle design and see how much they differ.
I've tried to get estimates from Quartus PowerPlay, eg., for the DE0-nano design, but the estimates do not match hardware measurements, so I have low confidence. The estimates were based on .vcd dumps from Modelsim, so they should have been accurate. The simulations for larger designs take forever, so using an evaluation kit is a more effective use of time.
Cheers,
Dave
Honored Contributor
