Altera_Forum
Honored Contributor
Honored ContributorPowePlay. I/O power and core static power
I'm trying to understand how PowerPlay works.
I use Quartus 10.1 sp1. I have two projects (A and B) that execute exactly the same task. These projects are implemented on the same FPGA (Cyclone IV) and use the same pins (same locations). The internal structure of the two circuits is however quite different ( B uses 15000 FF while A uses only 200 FF and some logic). The circuits A and B are simulated at gate level with the same testbench and produce exactly the same output! The output is stored on a .vcd file both for A and B. The testbench is long enough to properly stimulate all the internal paths of the circuits A and B. When I run the PowerPlay analyzer I get the power dissipation data. In both cases (A and B) the confidence metrics is defined as high. Below the summary of the reports. A Total Thermal Power Dissipation 92.66 mW Core Dynamic Thermal Power Dissipation 4.93 mW Core Static Thermal Power Dissipation 80.91 mW I/O Thermal Power Dissipation 6.81 mW B Total Thermal Power Dissipation 188.05 mW Core Dynamic Thermal Power Dissipation 85.36 mW Core Static Thermal Power Dissipation 89.14 mW I/O Thermal Power Dissipation 13.55 mW I have two questions. 1) Since the used pins are the same and the input and output transitions are also the same, why the I/O power is so different? 2) The circuits differ largely in the dynamic power dissipation and I do expect this. However there is also a huge amount of static power dissipation. Where this static power comes from? If these are internal FPGA circuits that cannot switched off why there is a difference between A and B? Thank you in advance for any hint.
