New Contributor
Super ContributorHard to decide without seeing the full test design. E.g. what is source of signal_in, what is SignalTap aquisition clock?
Generally, edge detection can only reliably work, if signal_in is driven (in case of doubt already registered) in same clock domain. Is it so?
External/foreign clock domain signals should be double registered before entering the edge detector.
New ContributorThanks for your reply.
SingalTap aquisition clock is the same as the clock registered singal_in and signal_out.
The source of singnal_in is in another clock domain, hence I add two flops synchronizer before it enter this clock domain.
I've already tried two method to fix this bug but I still haven't got a clue why this bug happen.
The first one is latch the signal_in_pulse by register instead of combinational logic.
----- Source code----
// signal in positive edge detect
always @ (posedge clock) begin
if(!reset)
signal_in_r <= 1'b0;
signal_in_pulse <= 1'b0;
else
signal_in_r <= signal_in;
signal_in_pulse <= signal_in & ~signal_in_r
end
----- Source code----
The second one is set the reset as asychronous reset for these flipflops.
----- Source code----
// signal in positive edge detect
always @ (posedge clock or negedge reset) begin
if(!reset)
signal_in_r <= 1'b0;
signal_in_pulse <= 1'b0;
else
signal_in_r <= signal_in;
signal_in_pulse <= signal_in & ~signal_in_r
end
----- Source code----
