post synthesis verilog

hello,

i'm a beginer with quartus tool. actually i'm asking if it is possible to generate a post synthesis file written in verilog.i made a research and i found that it is possible to do it by using the following command:

quartus_eda <project_name> -c <revision name> --simulation --tool=<tool> --format=<verilog>

but with this method there are two problems. the first one is the necessity to do the fitter task (place and route) before generating such file.

the second problem that it is necessary to choose the tool which we will use .for exemple if we choose modelsim, so the generated verilog file should used only with modelsim. but for me i need a verilog file which is standard,so i can use it with any tool.

my last question is about the buffers added on I/O. i know that their is an option which allow the synthesizer to add buffers on every I/O, so i need to desactivate this option because i will add those buffers manually.

thank you in advance