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Altera_Forum's avatar
Altera_Forum
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14 years ago

post synthesis verilog

hello, i'm a beginer with quartus tool. actually i'm asking if it is possible to generate a post synthesis file written in verilog.i made a research and i found that it is possible to do it by ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

to generate a post map, try going to Assignments > Settings > EDA Tool Settings > Simulation > More EDA Netlist Writer Settings and turn on Generate netlist for functional simulation only. i'm not sure what the related .qsf setting is

i think the netlist gets written into simulation/<tool name>, i would expect the .vo to work in any simulator. the exception is probably the encrypted Stratix V models which are vendor specific