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Altera_Forum's avatar
Altera_Forum
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12 years ago

Post Synthesis Netlist

I'm refreshing myself on Quartus tool flow (haven't used it in years), and was wondering how to generate the Post Synthesis Netlist file for use in simulation. According to QTS_QII51008 (Figure 16-1), I should be able to generate it right after synthesis. However, within the tool, the only option I seem to find is to use EDA netlist writer to generate it, which requires the Fitter to run (which takes over 2 hours for my current design). I'm currently validating functionality and constantly adding in changes, and would like to avoid a 2-hour turnaround time to validate each change. Is it possible to generate a post-synthesis netlist by ONLY running synthesis?

FYI, I have found the following similar thread:

http://www.alteraforum.com/forum/showthread.php?t=23339

...which indicates that I should set "Generate Netlist for functional simulation only". However, this still seems to require Fitter to run.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Why are you doing a post synth simulation, and not an RTL simulation to validate your changes?

    With good design practice and good timing specs you should never need a timing simulation. RTL simulations run MUCH faster than post synth/fit simulations.

    10 years in FPGA design - not a single netlist simulation yet...