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jihunmoon's avatar
jihunmoon
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4 years ago
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post simulation does not support cyclone V?

hi, i want to use post synthesis simulation (such as gate level simulation) in quartus.

I need sdo file from quartus to open in modelsim. But I couldn't make sdo file and use this function with cyclone V in quartus. I read the quartus user guide and it said that post simulation doesn't support cyclone V. So I made sdo file and open it in modelsim with cycloen IV device.

I have a question. I think many people use cyclone V device, so is there a no way to use post simulation with cyclone V device??

I 'm not saying about timing analysis in quartus. I'm saying about the post-sim using quartus and modelsim.

3 Replies

  • Hi @jihunmoon

    Gate-level timing simulation is supported only for the Arria II GX/GZ, Cyclone IV, MAX II, MAX V, and Stratix IV device families.

    Unfortunately, the gate-level timing simulation is not supported for Cyclone V device.

    We recommend that you use Timing Analyzer rather than gate-level timing simulation with any simulator.

    Reference:

    https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-tp-simulation.pdf#page=5

    You may checkout the User Guide below on how-to use the Timing Analyzer:

    https://www.intel.com/content/www/us/en/programmable/documentation/ony1529966370740.html

    The tool is useful in analysis you design and to meet timing.

    Best Regards,
    Richard Tan

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

      • RichardT_altera's avatar
        RichardT_altera
        Icon for Super Contributor rankSuper Contributor

        You're welcome.

        I’m glad that your question has been addressed. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

        Best Regards,
        Richard Tan

        p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.