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Altera_Forum
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15 years ago

'Post-map' matches 'rtl functional' but differs from 'post-fit'

Can you tell me why post-fit (quartus_fit) mismatches the post-synthesis (quartus_map) simulation? I had a design with counter. A test bench waits for CLK to release the reset. This works in post-sy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Have you tried doing this again without using the buffer port type? Its hardly used by anyone, and not really the standard way to create output registers. Usually you would use an internal signal to store the value and assign an output to the internal signal. Another thing I notice is that in your code you have 2 separate if statements resetting the counter. It would be more common to use something like: 

 
  if CNT= 1000 or START = '1' then   
    CNT <= 0;
  else
    CNT <= CNT + 1;
  end if;