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Can you please refer to a respective VHDL specification. I'm not aware of it.
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I have never seen the specifictaion. Have you? Nevertheless, VHDL people know that VHDL was designed for simulation. On assignments + delta delay, take a book. (
http://books.google.com/books?q=delta+delay+assignment+vhdl&btng=search+books)
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I'm not motivated to assemble snippets.
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The "snippets" elaborate anoter, negative values related, issue of post-fit. The solid example of topic issue was given is second post before you responded. The two files cannot be joined just because one is synthesized while another is a test bench.
Thank you for telling that you are motivated only to instruct us in the topic, as you do not stop to confess, you understand weakly.
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In my understanding, a delta cycle occurs after updating the signals of all processes.
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After university cource and some experience I was left with the same impression. Unitl, I run into this
http://groups.google.ee/group/comp.lang.vhdl/browse_thread/thread/5e5801f51a375fe1 recently.
Honored Contributor
