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Altera_Forum
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15 years ago

'Post-map' matches 'rtl functional' but differs from 'post-fit'

Can you tell me why post-fit (quartus_fit) mismatches the post-synthesis (quartus_map) simulation? I had a design with counter. A test bench waits for CLK to release the reset. This works in post-sy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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People must know that an assignment incurs a delta delay.

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Can you please refer to a respective VHDL specification. I'm not aware of it.

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Huh? Try some magnifying glass!

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I'm not motivated to assemble snippets.

P.S.: In my understanding, a delta cycle occurs after updating the signals of all processes. I don't see a clear conclusion of this rule affecting the treatment of START in the said case. But I'm not an expert for simulation related VHDL. In synthesized VHDL, the question is meaningless, I think.