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In my understanding, start <= '1' (without the optional timed wait) is generated simultaneously with the clock edge. According to VHDL spec, the simulator may update both processes and the DUT instance in arbitrary order. Only an intentional delay assures a specific order of execution. The unspecified order problem is present in any functional simulation
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Perhaps my problem is because Altera people have not heard of the
delta delays concept that the whole VHDL simulation is based upon. People must know that an assignment incurs a delta delay.
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If you suspect a particular problem with Quartus simulator or design compiler, you should show an example, that allows to reproduce the problem.
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Huh? Try some magnifying glass!
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