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Where do you see them changed simultaneously?
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In my understanding, start <= '1' (without the optional timed wait) is generated simultaneously with the clock edge. According to VHDL spec, the simulator may update both processes and the DUT instance in arbitrary order. Only an intentional delay assures a specific order of execution.
The unspecified order problem is present in any functional simulation, I think. In timing (gate level) simulation, the START input may or may not have sufficient hold time related to CLK.
P.S.: I don't exactly understand about the other simulation issues. If you suspect a particular problem with Quartus simulator or design compiler, you should show an example, that allows to reproduce the problem.
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