Possible compilation error of nested if statements in VHDL

Hello!

Is there any implicit difference between nested "if" statements in the process block under "'event" and single "if" utilizing "and product"?

For some unknown (to me) reason the commented "if" produces an expected netlist of upper bounded counter, but the nested "ifs" that follows do not. They seems to result in some confusing "highest bit setter" (with two sequential muxes on reg D input) that sets frame_reg to ('high => '1', others => '0'), and that is all the logic does.

Can it be the case of an error in compiler that mistakenly tries to instantiate some priority encoding logic?

Or is it a known behaviour?

Or maybe it is a VHDL feature?

Thank you in advance.

frame_wren <= '1' if another_cnt = to_unsigned(12, another_cnt'length) else '0';
process(reset_n, clk, clk_ppu_en, frame_reg, frame_wren)
begin
    if reset_n = '0' then
        frame_reg <= (others => '0');
        
    elsif clk'event and clk = '1' then
--     if clk_ppu_en = '1' and frame_wren = '1' and frame_reg(frame_reg'high) = '0' then
--            frame_reg <= frame_reg + 1;
--     end if;
        if clk_ppu_en = '1' then
           if frame_wren = '1' then 
               if frame_reg(frame_reg'high) = '0' then
                   frame_reg <= frame_reg + 1;
               end if;
           end if;
       end if;
    end if;
end process;