Possible compilation error of nested if statements in VHDL

I see, but in my case there is now other signals in ifs. And I believe, this constructs, when synthesized, must behave exactly the same way (not paying attention to timings).

But they don't :( I checked it many times on harware (Cyclone II on DE2 board) trying to find out why does so simple component produce so strange results.

The RTL View shows that the single "if" construct is compiled into an "and" gate that feeds the clk_en input as expected, but the second one is not. The compiler generates some strange two-stage MUX feeding data input of the register, but mux doesn't select between reg and reg+1, but rather '1' & reg(reg'high-1 downto 0) and reg+1 (or something alike).

Does it sound like a compiller bug? Should I post my findings elsewhere?