Possible compilation error of nested if statements in VHDL

When you nest if's like you have done, you are implying priority.

Because you could have extra code inside each if statement, the extra "enable" output is needed for each.#

for example:

if clk_ppu_en = '1' then
  a <= ip;
    if frame_wren = '1' then 
      b <= ip2
    if frame_reg(frame_reg'high) = '0' then
      frame_reg <= frame_reg + 1;
    end if;
  end if;
end if;

When you check the netlist - are you checking the RTL view, or the map view? The fitter may be able to collapse the nested ifs into a single boolean equation.