Porting GPU optimized OpenCL code to Altera FPGAs

For a start it depends upon whose FPGA you will use. If it is an Altera board you have a good chance that it might work "as is" without changes to the code, with Xilinx this is highly unlikely as they need directives added to the code to help SDAccel. You are at least starting with the right hardware.

The configuration delays are not normally excessive but it depends on how many kernels you have. The recommendation for FPGA is to structure the kernel as a single work-item. This is somewhat different from the code you will be used to writing as this is likely to be vector-based to get the best out of the GPU. With an FPGA the resources are flexible and so the use of pipes will help to create a single work-item (if possible) or to at least to minimise the transfers from host to kernel and back.