I am instantiating these in a custom component. My instantiation reads as follows:
DFFEAS_inst : DFFEAS
port map
(
Q => f_signal(i)(j), -- Data output
CLK => i_clock, -- Clock input
ENA => '1', -- Clock enable input
D => i_sigin(j), -- Data input
SCLR => i_reset -- Synchronous reset input
--S => '0' -- Synchronous set input
);
I do not attempt to use any devclrn port or devpor port but still get the 'port devclrn does not exist in primitive "dffeas" ' / 'port devpor does not exist in primitive "dffeas" ' errors
I went ahead and added them thinking maybe making them explicit would help it connect them. The new instantiation reads as follows:
DFFEAS_inst : DFFEAS
port map
(
Q => f_signal(i)(j), -- Data output
CLK => i_clock, -- Clock input
ENA => '1', -- Clock enable input
D => i_sigin(j), -- Data input
SCLR => i_reset, -- Synchronous reset input
--S => '0' -- Synchronous set input
--+---------------------------------------------------------------------------
DEVCLRN => '1',
DEVPOR => '1'
);
I still get the same error.
The definition found in [quartus installation dir]/libraries/vhdl/alteradirectory/altera_primitives_components.vhd has both of those signals and the spelling is correct. not explicitly connecting them shouldn't cause an error especially since they have a default value. The definition of the primitive reads as follows:
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
dont_touch : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*" );
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic );
end component;
As you can see the spelling is correct and the signals exist in the primitive library definition. As well as the error occurs even when I do not use those ports.
My library calls read:
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_primitives_components.all;
New Contributor
