Port "data0" does not exist in primitive "and2" of instance "U1"

Dear my best friends

library IEEE;
use work.all;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity JKFF_TFF is
port 	(x,xp	: In STD_LOGIC;
		Z		: Out STD_LOGIC;
		clk		: In STD_LOGIC);
end JKFF_TFF;
architecture structure of JKFF_TFF is
Signal 	a1,a2				:  STD_LOGIC;
Signal	o1,o2,o3,o4			:  STD_LOGIC;
Signal	Y0,Y1,Y2,Y3,Y4		:  STD_LOGIC;
Signal	Q0,Q0p,Q1,Q1p,Q2,Q2p:  STD_LOGIC;
Begin
U1: Entity and2 port map (x,Q1p,a1);
End structure;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY and2 IS
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END and2;
ARCHITECTURE SYN OF and2 IS
--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC ;
	SIGNAL sub_wire2	: STD_LOGIC ;
	SIGNAL sub_wire3	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
	SIGNAL sub_wire4	: STD_LOGIC ;
BEGIN
	sub_wire4    <= data0;
	sub_wire1    <= sub_wire0(0);
	result    <= sub_wire1;
	sub_wire2    <= data1;
	sub_wire3(1, 0)    <= sub_wire2;
	sub_wire3(0, 0)    <= sub_wire4;
	lpm_and_component : lpm_and
	GENERIC MAP (
		lpm_size => 2,
		lpm_type => "LPM_AND",
		lpm_width => 1
	)
	PORT MAP (
		data => sub_wire3,
		result => sub_wire0
	);
END SYN;