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Altera_Forum's avatar
Altera_Forum
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15 years ago

Poll: Do you want the internal simulator back?

One of the changes in Quartus 10.0 is the missing of the internal simulator. As some people here wanted a poll: Here we go... BTW: I have started a similar poll regarding the lpm-functions in t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You'll have to do a gate level simulation; when you compile your design Quartus will produce a VHDL/Verilog model

Also, Xilinx has an app (XPort) which can convert AHDL into a VHDL netlist.