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Honored Contributor
Honored ContributorPLL Simulation not working fine
Hello, I am using Quartus Prime 17.0 version. In that when I am using PLL IP for clock generation, then during simulation I am not getting continuous clock at the output rather getting continous c...
Altera_ForumHonored Contributor
Honored Contributorwhat is the status of the locked signal? could be that the PLL has not locked yet.
Otherwise, is there a real need to simulate the PLL in your testbench? It can often take a long time to lock and can be rather slow. If your UUT is something other than PLL, its usually easier just to generate the clocks in the testbench.
