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Altera_Forum's avatar
Altera_Forum
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16 years ago

PLL reconfiguration not accepted

I'm having problems with a small part of a pretty big design. I want to phase shift a PLL output (Stratix II) and have instantiated megafunctions for PLL and PLL_RECONFIG and connected them like this...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I found it, not sure which of the following measures that fixed it though:

Proper reset of altpll_reconfig (old one didn't need this)

Have a scan chain memory initialization file for the altpll_reconfig block

Slowed down reconfiguration clock from 20 MHz to ~1MHz