PLL Reconfiguration Fails when built using Quartus v13.1

Hi All,

I have a Stratix III design where I use PLL to drive LVDS transmitters. The PLL is reconfigurable using an instantiation of the ALTPLL_RECONFIG IP along with mif-initialized ROMs. For an LVDS application in Stratix III, certain PLL outputs (C0, C3, C5) must be used. The design has worked fine for quite some time using Quartus 12.0 and also earlier versions.

So here is strange part. I recently installed Quartus 13.1 and if I build it with that tool, the design no longer works. If I do my normal RTL simulations, all is fine. After creating a simplified and lower-speed project, I did a gate-level simulation and see that the reconfig function is loading the correct divider values into the wrong (unused) PLL counters and bypassing (= divide by 1) the PLL counters I am using. This agrees with my hardware measurements. Each of the outputs I use should be divided down from the VCO frequency but instead is running at the VCO frequency.

As a side note, evidently Quartus sometimes re-arranges counters on purpose but the documentation says this will not occur if the design includes reconfiguration. To be sure, I added the "Preserve PLL Counter Order" assignment but this changed nothing.

I have already submitted a service request but while waiting for that to get somewhere I thought I would put this out and see if anyone else has a similar experience? If I get a resolution from the service request, I'll post a follow-up here.