PLL Reconfiguration Fails when built using Quartus v13.1

Altera has come back with a solution. They have instructed me to put a file named "quartus.ini" in the project folder. The contents of the file are simply "ftm_absorb_inverts_new=off". (without the quotes) When I do that and build with Quartus 13.1, RTL & gate level sims work normally, and the design works in actual hardware as well. They tell me the fix should be included in Quartus 14 so I can discontinue using the workaround at that point.

To "fpgabuilder", your problem might be similar to mine. My design uses dynamic phase shifting too but since the port counters were mixed up, the design crashes and burns before I can see if the dynamic phase shifting was working or not.