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I have not tried changing the reconfiguration clock frequency but it is well within the specified range. For the Stratix III, the range is specified on the data sheet (under Switching Characteristics => Core Performance Specs => PLL => scanclk frequency) and is 100 MHz maximum with no minimum. This example project used 50 MHz, while my actual target design uses 80 MHz. Both work OK when built with Quartus 12.0. Thank you for the suggestion, that would have been an easy fix.
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No problem and thanks for pointing out the switching frequency spec which I must have overlooked! Reply back with what Altera finds. Also, in case you haven't seen it, there was an update 4 for Quartus recently, but I don't think there would be anything useful for this issue.
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