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Randolina,
It sounds like you may have a separate problem. I tried changing my project so the PLL uses only one output and did a gate-level simulation. (gate-level simulation simulates my problem, RTL level does not) My results were similar to before, the reconfiguration happens but the divider that I was using (c0) gets bypassed and the divider values intended for c0 get written to the unused c1 divider instead. In all cases, the PLL is running at exactly the correct frequency, there is no few MHz error.
The Stratix III PLL that I am using is an integer PLL, not fractional, so we are dealing with substantially different PLLs.
By the way, Altera has replicated my problem but does not yet have a solution.
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Glad to hear they could replicate it on their end too. I've only recently started using the PLL reconfiguration block and one mistake I made was clocking the altera_pll_reconfig too fast. I was trying to run it at my system clock which is 125MHz, but this caused issues where it would sometimes reconfigure the frequency. I did not see a timing spec for the altera_pll_reconfig block. I brought it down to 25MHz and can successfully reconfigure the frequency each time. I've tried as low as 10MHz to see if it would help the dynamic phase shift problem, but it still did not work. Even through it worked in a previous Quartus version, have you tried lowering the clock going into your reconfiguration block just as a test?
The Cyclone V looks like they combined the fractional PLL with the integer PLL by adding their Delta Sigma Modulator shown in the picture. The details under the hood between the Stratix III and Cyclone V fractional/integer PLL may be very different like your said though.
https://www.alteraforum.com/forum/attachment.php?attachmentid=8676
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