PLL Reconfiguration Fails when built using Quartus v13.1

Randolina,

It sounds like you may have a separate problem. I tried changing my project so the PLL uses only one output and did a gate-level simulation. (gate-level simulation simulates my problem, RTL level does not) My results were similar to before, the reconfiguration happens but the divider that I was using (c0) gets bypassed and the divider values intended for c0 get written to the unused c1 divider instead. In all cases, the PLL is running at exactly the correct frequency, there is no few MHz error.

The Stratix III PLL that I am using is an integer PLL, not fractional, so we are dealing with substantially different PLLs.

By the way, Altera has replicated my problem but does not yet have a solution.