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Hi All,
I have a Stratix III design where I use PLL to drive LVDS transmitters. The PLL is reconfigurable using an instantiation of the ALTPLL_RECONFIG IP along with mif-initialized ROMs. For an LVDS application in Stratix III, certain PLL outputs (C0, C3, C5) must be used. The design has worked fine for quite some time using Quartus 12.0 and also earlier versions.
So here is strange part. I recently installed Quartus 13.1 and if I build it with that tool, the design no longer works. If I do my normal RTL simulations, all is fine. After creating a simplified and lower-speed project, I did a gate-level simulation and see that the reconfig function is loading the correct divider values into the wrong (unused) PLL counters and bypassing (= divide by 1) the PLL counters I am using. This agrees with my hardware measurements. Each of the outputs I use should be divided down from the VCO frequency but instead is running at the VCO frequency.
As a side note, evidently Quartus sometimes re-arranges counters on purpose but the documentation says this will not occur if the design includes reconfiguration. To be sure, I added the "Preserve PLL Counter Order" assignment but this changed nothing.
I have already submitted a service request but while waiting for that to get somewhere I thought I would put this out and see if anyone else has a similar experience? If I get a resolution from the service request, I'll post a follow-up here.
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I am having a different issue with the ALTPLL_RECONFIG_IP which I was told was related to my Cyclone V silicon revision. I only have a single output of the PLL that I am reconfiguring. I am able to adjust the frequency as desired if I have 1 output, but the phase shift does not work correctly. It will phase shift in one direction by twice the amount than expected. Trying to shift in the reverse direction does not move the PLL output at all.
I did notice if I add a second output to my PLL, the frequency reconfiguration gets some strange results where the output frequency is off by a few MHz than what I tried to reconfigure it as. Since my service request was initially opened back in November 2013, I have a newer silicon revision that is experiencing the same exact problems (even though it should be fixed in this new silicon revision).
Just as an experiment, did you try disabling all your other PLL outputs and only use C0? I'm curious if you are able to reconfigure the frequency when only one output is enabled. I am using Quartus 13.1 update 3 on Windows 7.
Another side note - I just noticed that my Fractional PLL output drifts at about 1ns per minute with respect to the reference clock if the Dynamic reconfiguration mode is enabled. The drift is smother with the DSM set to 3rd order and jumpier if the DSM is set to 1st order. I have just submitted a service request. Have you seen a similar result? I attached a screenshot of my simplified test project:
https://www.alteraforum.com/forum/attachment.php?attachmentid=8637
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