PLL is not fully compensated

Hello JwChin

now, I think I understand the problem here. First of all the diagram you showed is the Post Fitting Map Viewer. This is quite importand because the other viewers does not show this contolblock at all!

Second, the showed controlblock is not part of my design and therefore I focused on the assignment editor. Here I have seen that the FPGA_CLK1 has been set as "global signal" and was enabled. Therefore

Quartus put in such controlblock before the PLL!

After disabling it the warning messages is gone and everything fine :)

Thank you!