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Norick's avatar
Norick
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7 years ago

PLL is not fully compensated

Hello in Quartus I get following warning message (same message for PLL_FRT and PLL_ADC_intern): Warning: PLL "PLL_FRT:PLL_FRT_inst|PLL_FRT_altpll_0:altpll_0|PLL_FRT_altpll_0_altpll_nr22:sd1|pll7" i...
JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi @Norick​

I am referring to the CLKCTRL before the PLL. See screenshot.

Maybe is the way you instantiate your block that puts the CLKCTRL there.

As for the ClockControlblock after the PLL, that is not related to the warning.

  • Norick's avatar
    Norick
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hello JwChin

    now, I think I understand the problem here. First of all the diagram you showed is the Post Fitting Map Viewer. This is quite importand because the other viewers does not show this contolblock at all!

    Second, the showed controlblock is not part of my design and therefore I focused on the assignment editor. Here I have seen that the FPGA_CLK1 has been set as "global signal" and was enabled. Therefore

    Quartus put in such controlblock before the PLL!

    After disabling it the warning messages is gone and everything fine :)

    Thank you!

    • JonWay_altera's avatar
      JonWay_altera
      Icon for Frequent Contributor rankFrequent Contributor
      7 years ago

      You are welcome. I am glad it helped! 😊