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Norick's avatar
Norick
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7 years ago

PLL is not fully compensated

Hello in Quartus I get following warning message (same message for PLL_FRT and PLL_ADC_intern): Warning: PLL "PLL_FRT:PLL_FRT_inst|PLL_FRT_altpll_0:altpll_0|PLL_FRT_altpll_0_altpll_nr22:sd1|pll7" i...
JonWay_altera's avatar
JonWay_altera
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7 years ago

Hi @Norick​

On the other side you changed the origin design and cut off the clock control block (see orign file at the top again). Of course without clock control block the warning dissapear but again it is a different design.

==> Yes, that's what im trying to say. It is the clock control block that is causing the problem. Thus, my recommendation is to instantiate as "B" (not A), you shouldnt have a CLKCTRL block in between. The CLKCTRL routes to a clock network, e.g. GCLK before going to the PLL. Thus the warning.

If you want to avoid the warning, connect the dedicated input clk pin directly to PLL (without CLKCTRL in between).

  • Norick's avatar
    Norick
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    7 years ago

    Hello JwChin

    you say "connect the dedicated input clk pin directly to PLL (without CLKCTRL in between)" but in my design I have the PLL followed by the clock controlblock.

    The idea is to power down the clock network after the PLL in order to minimize the power consumption. How would you do this?

    Thanks