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Norick's avatar
Norick
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7 years ago

PLL is not fully compensated

Hello in Quartus I get following warning message (same message for PLL_FRT and PLL_ADC_intern): Warning: PLL "PLL_FRT:PLL_FRT_inst|PLL_FRT_altpll_0:altpll_0|PLL_FRT_altpll_0_altpll_nr22:sd1|pll7" i...
JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi @Norick​

A is the block symbol you created. I can see the same error as you mentioned.

B is the bsf symbol i created from your qsys file. B works fine on my end.

I am not sure how you created BlockA, but that seems to put a clkctrl block in between your input pin and pll. Thus the warning message.

In BlockB, you can see that the clock pin is connected directly to the PLL. You wont see the warning message.

I attached the QAR which BlockB is created in pllgenjwtop.bdf (as top file).

  • Norick's avatar
    Norick
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hello

    well I do not see any difference between A and B as you mentioned (see yellow marking in B). The only difference is that you are using clk5 - that's all. On the other side you changed the origin design and cut off the clock control block (see orign file at the top again). Of course without clock control block the warning dissapear but again it is a different design.

    Therefore I am still confused about the warning message... could you please use my posted design and change it in order to get rid of the warning message? Therefore we have the same design from scratch and a solution would be clear.

    The PLL Block (see A) is the same as your B. The difference is that I insert it in the scheme as "Insert symbol as block".

    thanks