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Norick's avatar
Norick
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7 years ago

PLL is not fully compensated

Hello in Quartus I get following warning message (same message for PLL_FRT and PLL_ADC_intern): Warning: PLL "PLL_FRT:PLL_FRT_inst|PLL_FRT_altpll_0:altpll_0|PLL_FRT_altpll_0_altpll_nr22:sd1|pll7" i...
JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi @Norick​

I created a simple design based on your description (attached). It all compiled correctly. Im using Standard Edition, though.

At the least, you can compare the difference. If possible, test with Standard Edition.

As for your question:

  • Do I need to assign a specific PLL to my clock input? If yes, how can I do it?

Ans: No, you dont have to specify the PLL. Based on your RTL connection, fitter will know the input pin is routed to which PLL.

Norick's avatar
Norick
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7 years ago

Hello JwChin

thanks for the answer and the test-project. The problem I am dealing with, is that I get following warning message:

Warning: PLL "PLL_FRT:PLL_FRT_inst|PLL_FRT_altpll_0:altpll_0|PLL_FRT_altpll_0_altpll_nr22:sd1|pll7" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

The question here is:

  • why I get this warning and how can I eliminate it?
  • What is the meaning of "non-dedicated input" for my PLL if the fitter selects the right PLL?

Thanks