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Norick's avatar
Norick
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7 years ago

PLL is not fully compensated

Hello in Quartus I get following warning message (same message for PLL_FRT and PLL_ADC_intern): Warning: PLL "PLL_FRT:PLL_FRT_inst|PLL_FRT_altpll_0:altpll_0|PLL_FRT_altpll_0_altpll_nr22:sd1|pll7" i...
JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi @Norick,

Which quartus version?

Which device? PN needed.

Which pin?

It would be great if you can attached a simple design that shows the problem here.

Norick's avatar
Norick
Icon for New Contributor rankNew Contributor
7 years ago

I am using:

  • Quartus: 18.0.0 Build 614 Lite Edition
  • Max10 10M40DAF256I7G

The used pins of the Max10 are:

  • FPGA_CLK1 --> Max10 Pin_K6
  • FPGA_CLK2 --> Max10 Pin_J11

The design is shown above. At the moment there is NO special assignement done in order set a specific PLL to a specifif clock source!

Question:

  • Do I need to assign a specific PLL to my clock input? If yes, how can I do it?

Thanks