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Altera_Forum
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15 years ago

PLL input from non-dedicated clock pin

Hello all, I've struck with a simple problem and I'm almost nearing the wall in terms of options. I've a design in which the clock is coming from a non-dedicated clock pin (PIN_AJ16). I've...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I've to run module A at half of the Clk2 frequency. I've not depicted the divider because I'm not sure which is the best way to go about

1. Ripple clock divider

2. Gate the Clk2 before module A (Now there will be 2 enables, one outside module A, one is already inside, I hope it will not be an issue)

I've already tried 1 (saw some hold slack issues) and will give 2 a shot.